IMS Instructional Center
1. ABOUT INSTRUCTIONAL CENTER

The Georgia tech IEN provides an instructional lab facility to support advanced training and lab courses taught in the area of CMOS fabrication, MEMS fabrication, and micro/nanoelectronic processing. The facility located in the Joseph M. Pettit building consists of an 1100 ft2 Instructional Cleanroom (class 100) and a 340 ft2 Device Characterization Lab for wafers and bare chips.

WHAT WE OFFER:

  • Lab courses

We provide a group of lab training sessions to students who are interested in microfabrication processes from a wide variety of departments such as Electrical Engineering, Mechanical Engineering, Chemical and Biomolecular Engineering, Biomedical Engineering, etc. The lab sessions are provided as a part of accredited College of Engineering lecture courses. Students of the CoE courses are divided into small groups and have unique hands-on experiences of microfabrication in a cleanroom environment under an instructor’s expert guidance. The hands-on processes include:

  • Oxidation and Diffusion doping
  • Photolithography
  • Etching
  • Metallization
  • Wafer Probing
  • Electrical Testing of wafers and bare chips

 

  • Feasibility studies

Our expert staff can carry out feasibility studies to determine whether our CMOS-compatible micromachining technologies and device testing equipment are advantageous over other technologies. Our feasibility studies are carried out as follows:

  1. User provides us with a detailed problem description, constraints and desired outcome using the Request Assistance form
  2. Feasible processes and plan are suggested. A meeting is scheduled if needed.
  3. User provides us with samples for processing and testing
  4. Samples are processed
  5. Results are evaluated and sent to user
  6. User provides us with feedback

 

  • Development of device testing

Due to the versatile nature of device testing, users will work with a staff member in order to configurate the best setup and to determine parameters for the desired outcome. Most testing will be carried out with a probe station directly on wafers or bare dies. The challenges to the testing parameters are finding the appropriate configuration for each sample, including ground connection, voltage/current range, frequency range, impedance matching, etc.

Contact Information
Seung-Joon Paik, Ph.D.
Instructional Center coordinator
Senior Research Engineer
seung.paik@ien.gatech.edu
404-894-8807